In integrated circuit design, the via density requirement become imperative due to yield and reliability concerns. If either the metal or via density is not sufficient, the low-k material popularly used in advanced integrated circuits is not robust to Chemical-Mechanical Polishing (CMP) process or LD-free bumping process during manufacturing.
For a given integrated circuit design, usually placement and routing are performed by Place and Route (P&R) tools. By P&R, a layout of a larger block of the circuit or the whole circuit is created from layouts of smaller sub-blocks. The first step, placement, involves deciding where to place all electronic components, circuitry, and logic elements in a generally limited amount of space. This is followed by routing, which decides the exact design of all the wires needed to connect the placed components. This step must implement all the desired connections while following the rules and limitations of the manufacturing process.
Afterwards, dummy metal and dummy via insertion on the placed and routed design is performed by either a P&R tool or a design-rule-checking (DRC) utility. However, both methods have problems. If the P&R tool is used for dummy metal/via insertion, it requires long runtime, generates very big sized graphic data system (GDS) files, and could produce undesirable results due to algorithmic flaws of the conventional P&R tools. For example, a P&R tool treats every dummy via as a single instance in the GDS file, which contributes to the huge size of the GDS file. And no dummy via drops are allowed below or upon non-default-width dummy metal. Also, only a few via array structures are allowed because of execution time and database size necessary for the P&R tools to recognize and examine the design. Further, the insert-via-first method in P&R tools hinders potential dummy metal/via insertion later on, because of spacing and other rules.
On the other hand, if the DRC tool is used for dummy metal/via insertion, it requires large timing-checking loops for the design closure due to the timing-unawareness of DRC utility. The timing is the speed performance of the chip or integrated circuit design. The method that requires large timing-checking loops by using a DRC utility takes more time to finish the design.
Accordingly, new methods for dummy metal and dummy via insertion are desired that are faster and more flexible, provide sufficient via density, and reduce the GDS file size.